1. Field of the Invention
The present invention relates to a multi-level quadrature amplitude modulation and demodulation system utilizing a D/A converter and an A/D converter.
2. Description of the Related Art
FIGS. 1A and 1B form a block diagram of a prior art modulation and demodulation system (64-level, in this example). FIG. 1A illustrates a transmitter having input terminals for receiving six 2-level binary input digital signals (i.e., data for each channel) D1IN-D6IN which are rearranged into two sets of signals, D1IN-D3IN and D4IN-D6IN. Each set includes three signals which are input to a corresponding one of digital/analog (D/A) converters 10a and 10b, in which the sets of signals are converted to 8-level amplitude modulated signals A1 and A2. The 8-level amplitude modulated signals A1 and A2 are supplied to a quadrature amplitude modulator 12 which provides a 64-level quadrature amplitude modulated signal over a transmission link by modulating the carrier after any necessary band-limitation.
FIG. 1B illustrates a receiver which is coupled to the QAM modulator 12 via the transmission link, and in which an input signal (i.e., the modulated signal) is input to a quadrature amplitude demodulator 14, and demodulated with a recovered carrier generated by a carrier recovery circuit (not shown). Demodulated outputs B1 and B2 are input to analog/digital (A/D) converters 16a and 16b, respectively, and a recovered clock CLK which is regenerated by the clock recovery circuit (not shown), is input to the A/D converters 16a and 16b. As a result, digital signals D1OUT-D6OUT are clocked out at output terminals as outputs of the A/D converters 16a and 16b in accordance with the clock.
The D/A converters 10a and 10b provide 3-bit binary numbers by extracting one bit from the three binary digital signals which are input, and convert such binary numbers to the analog signals A1 and A2 through D/A conversion. Each bit of the binary input digital signals D1IN-D3IN is processed as follows. D1IN is processed as the most significant bit of the 3-bit binary number, D2IN as the intermediate bit, and D3IN as the least significant bit. Therefore, the following table can be obtained for D/A conversion output A1.
TABLE 1 ______________________________________ D1IN D2IN D3IN Al ______________________________________ 1 1 1 7 1 1 0 6 1 0 1 5 1 0 0 4 0 1 1 3 0 1 0 2 0 0 1 1 0 0 0 0 ______________________________________
The processing explained above is also applied to the digital binary input signals D4IN-D6IN. The signals D1IN-D6IN are serial data supplied from terminals or channels (referred to herein only as channels) 1-6 (not illustrated). The channels are sequentially processed in accordance with the conversion explained above.
The multi-level quadrature amplitude modulation and demodulation system of the prior art has a problem in that an error rate due to distortion of the modulated signal, or noise on the modulated signal, results in differences between the paths D1OUT-D6OUT. As is apparent from Table 1, D1IN, D4IN are processed as the third digit of the 3-bit binary signal (i.e., a digit of "4"); D2IN, D5IN as the second digit (i.e., a digit of "2") and D3IN, D6IN as the first digit (i.e., a digit of "1"). Therefore, after conversion to an analog signal, D1IN, D4IN have an amplitude equal to 2 times that of D2IN, D5IN or 4 times that of D3IN, D6IN. Similarly, D2IN, D5IN have an amplitude equal to 2 times that of D3IN, D6IN. In the case of this system, the inputs D1IN, D4IN have the best path, inputs D2IN, D5IN have the second best path and inputs D3IN, D6IN have the worst path.